Peripheral data storage systems attached to large scale host processors employ direct access storage devices (DASD) which usually take the form of rotatable magnetic memory devices. For enhancing the performance a large random access memory cache is selectably interposed between the host processor and the DASD for enhancing the rate of data transfer between the host processor and the peripheral subsystem. That is, the cache tends to mask the latency delays of a DASD. Algorithms have been developed for handling the relationship between the host processor, the cache and the DASD; without such algorithms intervention of the cache could degrade the performance. Performance and integrity problems are always of concern. New controls and procedures are needed. Machine operations have been devised to solve these problems for those situations in which the data burst rate of the channel connecting the host processor to the peripheral subsystem approximates the burst data rate of the DASD. When a channel is used between the host processor and the peripheral subsystem which has a greater burst data rate then the DASD, other algorithms and controls are required for ensuring high performance while maintaining data and system integrity. A further problem is that the length of the channel cable between the host processor and peripheral subsystem is being made longer which means that the signal propagation time is increasing. With increased data rates, such increased signal propagation delays provide a significant decrease in performance when a number of control signals which cannot be overlapped in time have to be exchanged between the host processor and the peripheral subsystem.
It is common practice in cached peripheral subsystems to provide a so called "branching write". Such an operation transfers data from the host processor simultaneously to the DASD and to the cache. The control unit or controller allocates a new set of cache storage segments (a segment is an allocatable unit of storage within the cache) when the DASD switches from one track to another track that is not currently stored in the cache. If the cache is sufficiently full, there may be insufficient cache segments available for storing data for the upcoming track, particularly when it is time for the subsystem to switch from the current track to a next track. In the prior art, peripheral controllers effect track switching when not enough cache segments are available, cause a channel command retry (CCR), a known way of a peripheral controller communicating to a host processor. This communication indicates a delay in the upcoming data transfer and to resend the current command. The system waits for cache segments to become available. Then the peripheral controller reconnected to the channel for continuing with the branching write. Newer peripheral subsystems operate in a so-called non-synchronous mode in which the peripheral subsystem accepts data from the host processor for writing to cache and DASD and presents ending status to each command causing the transfer of data even though such received data is not in fact written to the DASD. Accordingly, when the subsystem process determines that a track switch is necessary and determines that insufficient number of cache segments are currently available further data is not received until after the CCR. At the time the CCR is sent to the host processor the peripheral subsystem may have already accepted data from the host processor for the upcoming track and already presented ending status to the host processor, i.e., indicating that the data is in fact stored on the DASD. The CCR ensures data integrity while not dedicating the channel to the one data transfer, i.e., such dedication decreases the channel utilization and thereby degrades total data processing system operation. A data integrity problem can occur if the channel, when dedicated, experienced a failure of some type with a result of loss of data in the peripheral subsystem. It should be remembered that peripheral data subsystems when supplying ending status to a host processor are in effect stating to the host processor that the received data is retentively stored in the peripheral subsystem. It is desired to provide an efficient and complete solution to the problem described above.